The present invention relates to the control of the electrical power supply for semiconductor logic circuitry, particularly but not exclusively to circuitry powered by one single battery down to 1 volt.
Battery economizing circuits are well known in the fields of manually portable apparatus such as radio paging receivers and transceivers used, for example, by the police, which transceivers have to remain in a standby mode for at least the duration of a shift and only be fully powered when a signal for the particular transceiver is to be made audible or a signal is to be transmitted. The design, construction and operation of such equipment is generally such that different sections of the equipment, such as audio amplifiers and power amplifiers, are switched-on and -off between, say zero volts, and the battery voltage and vice versa.
The above type of control is unsuitable for use with digital circuitry, especially low voltage circuitry such as I.sup.2 L, which operates between 0.8 V and 1.5 V and has a low current dissipation. This type of circuitry typically comprises two main component parts, unscaled logic which operates at the full voltage to process input and output signals and scaled logic which, for example, comprises a memory and is required to remain energized continuously, if necessary at a current below the full current value, in order to preserve the stored information.
Japanese Kokai 58-70333(A) discloses a two part circuit of which one part remains continuously energized while the power supply to the second part is switched-on and -off using a MOSFET. This Japanese publication does not suggest the possibility of operating the permanently energized circuit part at a lower current when the apparatus is in a standby mode, nor how the power should be controlled as it is switched-on and -off.
If the scaled logic is implemented as one or more integrated circuits then, unless care is taken in controlling the powering-up and -down of the integrated circuit, internal delays and parasitic capacitances can lead to the integrated circuits being brought to a state of readiness at different times, when measured in nanoseconds, so that data may be lost.